Dynamic Partial Reconfiguration Research Articles

On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)

Field Programmable Gate Arrays (FPGAs) have become increasingly popular in computing platforms. With recent advances in bitstream format reverse engineering, the scientific community has widely explored static FPGA security threats. For example, it is now possible to convert a bitstream to a netlist, revealing design information, and apply modifications to the static bitstream based on this knowledge. However, a systematic study of the influence of the bitstream format understanding in regards to the security aspects of the dynamic configuration process, particularly for Xilinx’s Internal Configuration Access Port (ICAP), is lacking. This article fills this gap by comprehensively analyzing the security implications of ICAP interfaces, which primarily support dynamic partial reconfiguration. We delve into the Xilinx bitstream file format, identify misconceptions in official documentation, and propose novel configuration (attack) primitives based on dynamic reconfiguration, i.e., create/read/update/delete circuits in the FPGA, without requiring pre-definition during the design phase. Our primitives are consolidated in a novel Stealthy Reconfigurable Adaptive Trojan framework to conceal Trojans and evade state-of-the-art netlist reverse engineering methods. As FPGAs become integral to modern cloud computing, this research presents crucial insights on potential security risks, including the possibility of a malicious tenant or provider altering or spying on another tenant’s configuration undetected.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles (UAVs) have been used for many applications including military, construction, image and video mapping, medical, search and rescue, wireless communications, and aerial surveillance. One key research topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process for UAVs is to combine inertial navigation system (INS) sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as natural phenomena (ionospheric scintillation) or malicious attacks (jamming or spoofing). One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce the computational load and processing time for image edge detection. The dynamic partial reconfiguration (DPR) of part of the SVR datapath was implementated to accelerate the process, reduce the area, and analyze its granularity aspect by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This kind of architecure with DPR also facilitates the low power consumption of 4 mW, leading to a reduction of 57 % compared with that without DPR, which is also the lowest power consumption compared with other machine learning (ML) hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel showed a success rate of 99.18 % and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.

Flare: An FPGA-Based Full Precision Low Power CNN Accelerator with Reconfigurable Structure.

Convolutional neural networks (CNNs) have significantly advanced various fields; however, their computational demands and power consumption have escalated, posing challenges for deployment in low-power scenarios. To address this issue and facilitate the application of CNNs in power constrained environments, the development of dedicated CNN accelerators is crucial. Prior research has predominantly concentrated on developing low precision CNN accelerators using code generated from high-level synthesis (HLS) tools. Unfortunately, these approaches often fail to efficiently utilize the computational resources of field-programmable gate arrays (FPGAs) and do not extend well to full precision scenarios. To overcome these limitations, we integrate vector dot products to unify the convolution and fully connected layers. By treating the row vector of input feature maps as the fundamental processing unit, we balance processing latency and resource consumption while eliminating data rearrangement time. Furthermore, an accurate design space exploration (DSE) model is established to identify the optimal design points for each CNN layer, and dynamic partial reconfiguration is employed to maximize each layer's access to computational resources. Our approach is validated through the implementation of AlexNet and VGG16 on 7A100T and ZU15EG platforms, respectively. We achieve an average convolutional layer throughput of 28.985 GOP/s and 246.711 GOP/s for full precision. Notably, the proposed accelerator demonstrates remarkable power efficiency, with a maximum improvement of 23.989 and 15.376 times compared to current state-of-the-art FPGA implementations.

Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

Fault tolerance is crucial for mission-critical FPGA-based systems in radiation environments. Soft-core processors in these systems, performing both control and computational tasks, require efficient soft error mitigation techniques to enhance their fault tolerance. In this paper, we investigate the variation trends in the fault tolerance of various processor components as the software workload changes. Based on our investigation, we propose a reconfigurable soft error mitigation framework that dynamically switches the hardening strategies for the processor according to the running workloads. The innovative application of dynamic partial reconfiguration technique in FPGAs enables time-multiplexing of the same circuit region to accommodate various hardening schemes, consequently achieving high area efficiency. We apply the framework to an open-source dual-issue superscalar RISC-V processor on a Xilinx ZCU102 FPGA board. Compared to traditional spatial redundancy-based hardening techniques, the proposed framework achieves a 20.84 % reduction in LUT utilization and a 20.53 % reduction in flip-flop utilization. The effectiveness of our framework has been evaluated through fault injection campaigns. The results indicate that, on average, only 0.05 % of faults would lead to system failure after hardening. Therefore, our work offers a new perspective on dynamic soft error mitigation in reconfigurable systems.

Evolvable Hardware Based Optimal Position Control of Quadcopter

Trading off performance metrics in control design for position tracking is unavoidable. This has severe consequences in mission-critical systems such as quadcopter applications. The controller area and propulsion energy are conflicting design parameters, whereas the reliability and tracking speed are related metrics to be optimized. In this research, a switching-based position controller was co-simulated with the quadcopter model. Performance analysis of the Field Programmable Gate Array (FPGA)-based controller validates a better scheme for tracking speed, propulsion energy, and reliability optimization under similar error performance. To improve the computation power and controller area, the dynamic partial reconfiguration(DPR) approach has been adapted and implemented on FPGA using the Vivado Integrated Development Environment (IDE), where a ranking-based approach brings into action either proportional derivative, sliding mode, or model predictive controllers for each dimension of position tracking. It is verified by analyzing the cumulative tracking speed, reliability, controller area, and propulsion energy metrics that the proposed controller can optimize all these metrics within three successive iterations of tracking either in the same direction or in any combination of directions. Concerning the implementation results of the controller with the switching-based controller, there is 6 % computation power and 30 % resource savings due to DPR .

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers.

Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables-RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

Task‐based preemptive scheduling on FPGAs leveraging partial reconfiguration

SummaryField‐programmable gate arrays (FPGAs) are an attractive type of accelerator for all‐purpose high performance computing computing systems due to the possibility of deploying tailored hardware on demand. However, the common tools for programming and operating FPGAs are still complex to use, especially in scenarios where diverse types of tasks should be dynamically executed. In this work, we present a programming abstraction with a simple interface that internally leverages high‐level synthesis, dynamic partial reconfiguration and synchronization mechanisms to use an FPGA as a multi‐tasking server with preemptive scheduling and priority queues. This leads to an improved use of the FPGA resources, allowing the execution of several different kernels concurrently and deploying the most urgent ones as fast as possible. The results of our experimental study show that our approach incurs only a 10 5% overhead in the worst case when using two reconfigurable regions, whilst providing a significant performance improvement of at least 24 21% over the traditional full reconfiguration approach.

Automated design and usage of the Fault-Tolerant dynamic partial reconfiguration controller for FPGAs

This article presents a new design automation method for Fault-Tolerant (FT) systems implemented on dynamically reconfigurable Field Programmable Gate Arrays (FPGAs). The method aims at minimizing the human interactions needed to incorporate FT mechanisms into an existing system. It starts with a source code of an original unhardened circuit. It continues by automated manipulation of the source code, algorithmic strategic selection of suitable FT techniques, design space exploration of candidate FT implementations, and selection of the resulting implementation. The method also includes efficient evaluation of achieved FT parameters performed on the target HW. As a novel approach working on the level of HW description languages is employed, the code modification is separated, which differentiates our method from others. The case study utilizing this method targets the design of an experimental FT dynamic partial reconfiguration controller for an FPGA. This controller is helpful for the restoration of faulty components due to a single-event upset on an FPGA. We used the method to generate a set of Pareto-optimal controllers concerning the design’s Mean Time to Failure (MTTF) parameter, power consumption, and size. Then, the FT controller is connected to several benchmark circuits, and the reliability parameters are evaluated at the entire system level. Our results show that by replacing the standard reconfigurable controller with our automatically-designed FT controller for one specific benchmark, the design size increased by 20.1%, and MTTF increased by 11.7%. However, the efficiency is highly dependent on the target system size, MTTF, and circuit functionality. We also estimate that a complex system defined by half a million configuration bits would improve MTTF by more than 50%.

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Partially dynamic reconfiguration (PDR) technology can accelerate the reconfiguration process and overcome hardware resource constraints when facing the challenge of high performance with respect to applications and resources constraints on field-programmable gate arrays (FPGAs). On FPGAs with PDR technology, the available on-chip Block RAM (BRAM) resources may not satisfy the memory requirements for all data. If we reserve more BRAM resources, then the total area of the dynamically reconfigurable region (DRR) that is used for calculation will decrease, with a reduction in system performance. We propose a memory-aware optimization framework to search for the optimal solution considering partitioning, scheduling, and floorplanning, where we make a tradeoff between performance and on-chip memory resources utilization. We then propose methods for memory allocation: An ILP model and a heuristic algorithm are provided to determine the minimum memory requirements and the number of corresponding memory blocks for data, as well as to determine whether the memory block with its stored data is assigned on-chip or off-chip by formulating the problem into a 0-1 knapsack problem and solving it using dynamic programming. Experimental results show that the memory-aware optimization framework and methods of memory allocation can increase the amount of on-chip data access to 29.65% of the total data volume with guaranteed performance.

Modular Hardware/Software Architecture for Edge Units in Highly Flexible Manufacturing Systems

With the increasing demand for individualized production and swift adaptability to changing market needs, new manufacturing system concepts emerge. Aiming for high flexibility and scalability, they rely on universal reconfigurable machines that can be used in various production steps by automatically changing tools and sensors. Consequently, the data processing infrastructure is required to support the frequent exchange of process-specific software applications, ranging from control and monitoring tasks to complex sensor data processing. This can be a major challenge when computation-intensive software is supported by hardware acceleration to achieve the desired performance or latency requirements. In this paper, we present an edge unit architecture that allows for hosting such applications while meeting the needs for modularity and reconfigurability. It builds upon a hypervisor to partition fixed processing resources among the applications. We present a mechanism that extends this partitioning to field-programmable gate arrays (FPGA) by using dynamic partial reconfiguration. This provides the option to deploy application-specific hardware accelerators with computation-intensive applications while maintaining modularity and on-line reconfigurability. We conclude the paper by pointing out the potential of the proposed architecture based on a use case for automated disassembly in a reconfigurable robotic cell.

Partial Dynamic reconfiguration and task sceduling framework for FPGA: A survey with concepts, constraints and trends

Generally the accelerators type identifies the edge computing performance hugely and it includes Integrated Circuit (IC), Graphical Processing Unit (GPU) and Field Programmable Gate Array (FPGA). Among these accelerator FPGAs are widely used in several edge computing areas since it has the ability to reconfigure and has high energy efficient. The consequence also comes out with the paradigm of scheduling efficiency on CPU’s (software tasks) and FPGA (hardware tasks). However the conventional schemes not entirely exploited the variations among hardware and software tasks which results in low scheduling efficiency. Therefore a task scheduling system is proposed on basis of fully active reconfigurable system. The scheduling efficiency for the proposed scheme can be increased by switching the task overheads and by predicting the execution time for hardware with minimum task switching times.

DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

For several new applications, FPGA-based computation has shown better latency and energy efficiency compared to CPU or GPU-based solutions. We note two clear trends in FPGA-based computing. On the edge, the complexity of applications is increasing, requiring more resources than possible on today's edge FPGAs. In contrast, in the data center, FPGA sizes have increased to the point where multiple applications must be mapped to fully utilize the programmable fabric. While these limitations affect two separate domains, they both can be dealt with by using dynamic partial reconfiguration (DPR). Thus, there is a renewed interest to deploy DPR for FPGA-based hardware. In this work, we present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Doing More with Less (DML)</i> – a methodology for scheduling heterogeneous tasks across an FPGA's resources in a resource efficient manner while effectively hiding the latency of DPR. With the help of an integer linear programming (ILP) based scheduler, we demonstrate the mapping of diverse computational workloads in both cloud and edge-like scenarios. Our novel contributions include: enabling IP-level pipelining and parallelization to exploit the parallelism available within batches of work in our scheduler, and strategies to map and run multiple applications simultaneously. We consider the application of our methodology on real world benchmarks on both small (a Zedboard) and large (a ZCU106) FPGAs, across different workload batching and multiple-application scenarios. Our evaluation proves the real world efficacy of our solution, and we demonstrate an average speedup of 5X and up to 7.65X on a ZCU106 over a bulk-batching baseline via our scheduling strategies. We also demonstrate the scalablity of our scheduler by simultaneously mapping multiple applications to a single FPGA, and explore different approaches to sharing FPGA resources between applications.

Intelligent Optimization Approaches for a Secured Dynamic Partial Reconfigurable Architecture-Based Health Monitoring System

In this work, an intelligent multi-objective optimization technique is proposed to optimize various parameters such as power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]) for a health monitoring system designed using the Secured Dynamic Partial Reconfiguration (SDPR) architecture. The cost-efficient Dynamic Partial Reconfiguration (DPR)-based field-programmable gate array (FPGA) is very useful for analyzing many applications such as automation and data processing. The novelty of this paper is to design a new intelligent SDPR (i-SDPR) module in order to achieve better performance in a health monitoring system by considering various performance parameters. The SDPR architecture is incorporated with two reconfigurable modules such as Encrypt and Authenticate, which results in an increase in the core power consumption ([Formula: see text]), computation time ([Formula: see text]) and area ([Formula: see text]). So, to improve the performance of the SDPR-based health monitoring system, there is a necessity to optimize the performance parameters and it is achieved through intelligent multi-objective evolutionary (MOEA) techniques. The intelligent multi-objective evolutionary techniques such as Niched-Pareto Genetic Algorithm (NPGA), Pareto Archived Evolution Strategy (PAES) and Pareto Envelope-based Selection Algorithm (PESA) have been considered for better optimization in the performance parameters. For the study, the free-to-use MIMIC-III dataset is taken, which contains critically admitted various intensive care unit patient data. The dataset is processed through any one of the multi-objective evolutionary operators till satisfying the conditions and then forwarded to implementation. The proposed architecture has been implemented and tested using Cyclone[Formula: see text] V SX SoC Development Kit. The comparative analysis of various performance parameters was done for the proposed i-SDPR with the existing techniques such as the DPR and SDPR approach to show the improvement. The results declare that the proposed techniques obtain better performance compared to the existing techniques.

A Power-Aware Real-Time System for Multi-Video Treatment on FPGA with Dynamic Partial Reconfiguration and Voltage Scaling

As the energy consumption is an evaluating factor for System-On-Chip (SOC) design, this paper presents a power-aware architecture for a real-time multi-video system on FPGA. This architecture aims to optimize power consumption for a multi-video system on ARM-based architectures. The proposed architecture uses dynamic reconfiguration and voltage scaling to create a power-aware system for real-time multi-video processing with minimal power dissipation. Dynamic partial reconfiguration was used to optimize the utilization of resources and reduce dynamic power consumption. Voltage scaling was also used to optimize dynamic power consumption, by configuring the blocks to use the minimum necessary voltage for normal operating conditions. The proposed architecture focused on the Zynq platform. The results showed power savings of up to 70% concerning performance and real-time constraints.

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Vulnerability evaluation on 16 nm FinFET Ultrascale+ MPSoC using fault injection and proton irradiation

The SEE vulnerability in two ways bitstream loading implementations on a dynamic partial reconfiguration (DPR) design is examined using fault injections and proton irradiations on a Xilinx 16 nm FinFET Ultrascale+ MPSoC. During fault injection, two kinds of soft errors are detected, they are system halt (SH) and calculation result error (CRE). In comparison, the detected errors are only SHs in the 100 and 80 MeV proton irradiations. Also, the critical bit error and cross sections are calculated in the fault injection and proton irradiation, respectively. The results signify that there is almost no difference in SEE vulnerability between the two ways of bitstream loading in DPR design.

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

A convolutional neural network (CNN) classifies images with high accuracy. However, CNN operation requires a large number of computations which consume a significant amount of power when implemented on hardware. Precision scaling has been recently used to reduce the hardware requirements and power consumption. In this paper, we present an energy-efficient precision-scaled CNN (EEPS-CNN) architecture. Furthermore, the Field Programmable Gate Array (FPGA) is reconfigured during run time using Dynamic Partial Reconfiguration (DPR). If the battery level decreases, the EEPS-CNN design with the most appropriate power consumption is configured on the FPGA. DPR enables recognition applications to run at a low power budget while sacrificing minor accuracy instead of termination. The proposed architecture is implemented on Xilinx XC7Z020 FPGA and is evaluated on three datasets: MNIST, F-MNIST, and SVHN datasets. The results show a 2.2X, 2.39X, and 2.38X reduction in the energy consumption, respectively, while using only 7 bits to represent all inputs and network parameters. The accuracy of the proposed EEPS-CNN is only 0.53%, 3.67%, and 0.88% less than 32-bit floating-point architectures for MNIST, F-MNIST, and SVHN, respectively. Moreover, the results show up to 92.91X and 4.84X reductions in the power and energy consumption of the proposed EEPS-CNN compared to related designs developed for the MNIST dataset.

Dynamic Partial Reconfiguration for Adaptive Sensor Integration in Highly Flexible Manufacturing Systems

As new production system concepts emerge to face an increasing demand for individualized production, sensor integration for Industry 4.0 functions is becoming a major challenge. Flexibility- and scalability-focused concepts rely on reconfigurable machines that automatically replace smart end effectors between production steps. To ensure adaptability to future demands, these smart components, comprising the main tool and sensors, are connected to the static part of the machine via a unified electro-mechanical interface. In robot-based concepts, these components are furthermore space- and weight-constrained and should be cost-optimized. With respect to sensor integration, this leads to the challenge of interfacing sensors using different communication protocols and electrical signal properties through a fixed, minimal set of signal lines. In this paper, an architecture for an adaptive sensor integration unit is presented, targeting highly flexible production systems. Leveraging dynamic partial FPGA reconfiguration to exchange communication logic and an extensible hardware module located in the static part of the machine, it efficiently supports alternating communication protocols over static signal lines. It thereby reduces the number of signal lines as well as the need for protocol conversion units in the exchangeable components. A prototype implementation using industrial bus protocols shows its suitability and is evaluated concerning relevant timing characteristics and resource usage.